MCIMX6U5EVM10AC i.MX 6UltraLite ARM Cortex-A7 MPU 528MHz 128KB L2 Cache 10/100 Ethernet 2x USB 2.0 8x UART Secure Boot Industrial Temp (-40°C to +105°C) Low Power Design

MCIMX6U5EVM10AC i.MX 6UltraLite ARM Cortex-A7 MPU @ 528MHz 128KB L2 Cache 10/100 Ethernet 2x USB 2.0 8x UART Secure Boot Industrial Temp (-40°C to +105°C) Low Power Design

Features

The i.MX 6Solo/6DualLite processors are based on Arm Cortex-A9 MPCore Platform, which has the following features:

• The i.MX 6Solo supports single Arm Cortex-A9 MPCore (with TrustZone)

• The i.MX 6DualLite supports dual Arm Cortex-A9 MPCore (with TrustZone)

• The core configuration is symmetric, where each core includes:

— 32 KByte L1 Instruction Cache

— 32 KByte L1 Data Cache

— Private Timer and Watchdog

— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor

The Arm Cortex-A9 MPCore complex includes:

• General Interrupt Controller (GIC) with 128 interrupt support

• Global Timer

• Snoop Control Unit (SCU)

• 512 KB unified I/D L2 cache:

— Used by one core in i.MX 6Solo

— Shared by two cores in i.MX 6DualLite

• Two Master AXI bus interfaces output of L2 cache

• Frequency of the core (including NEON and L1 cache), as per Table 8.

• NEON MPE coprocessor

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

The SoC-level memory system consists of the following additional components:

— Boot ROM, including HAB (96 KB)

— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)

— Secure/non-secure RAM (16 KB)

• External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume, cost effective handheld DRAM, NOR, and NAND Flash memory standards.

— 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and DDR3L-800 in i.MX 6Solo; 16/32/64-bit LP-DDR2-800, 16/32/64-bit DDR3-800 and DDR3L-800, supporting DDR interleaving mode for 2x32 LPDDR2-800 in i.MX 6DualLite

— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.

— 16/32-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces.

— 16/32-bit PSRAM, Cellular RAM

Introduction

The i.MX 6Solo/6DualLite automotive and infotainment processors represent the latest achievement in integrated multimedia-focused products offering high-performance processing with a high degree of functional integration. These processors are designed considering the needs of the growing automotive infotainment, telematics, HMI, and display-based cluster markets.

The processors feature advanced implementation of single/dual Arm®Cortex®-A9 core, which operates at speeds of up to 1GHz. They include 2D and 3D graphics processors, 1080p video processing, and integrated power management. Each processor provides a 32/64-bit DDR3/DDR3L/LPDDR2-800 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth®, GPS, hard drive, displays, and camera sensors.

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